The present invention relates to a semiconductor device and an electronic instrument including the same.
A low power consumption operation has been strongly demanded for a semiconductor device provided in a portable telephone (electronic instrument in a broad sense) which operates by using a battery. On the other hand, it is necessary for a portable telephone to perform advanced information processing such as image processing and communication processing. Therefore, the capacity of a memory has been increased in order to retain an increased amount of processing data. A dynamic random access memory (DRAM) is included in a semiconductor device provided in such a portable instrument, for example. In this case, power consumption may be reduced by causing the semiconductor device to appropriately transition to a standby mode.
In order to operate a semiconductor device, it is generally necessary to supply a clock signal to the semiconductor device. A clock signal having a desired frequency may be directly applied to a semiconductor device from the outside. As another method, a phased locked loop (PLL) circuit may be provided in a semiconductor device, and a clock signal having a desired frequency may be generated by multiplying a low-frequency clock signal supplied from the outside. In general, the method of providing the PLL circuit in the semiconductor device is used from the viewpoint of convenience of use.
When causing the DRAM to retain data, a refresh operation is required in order to prevent the retained data from being lost. However, when generating a clock signal by using the PLL circuit, even if the semiconductor device transitions to the standby mode aiming at reducing power consumption, the amount of power consumed by the PLL circuit and a refresh controller for performing the refresh operation of the DRAM cannot be ignored.
JP-A-6-60645 discloses a technology for reducing power consumption accompanying the refresh operation of the DRAM, for example. This technology utilizes the fact that current consumption during the refresh operation in a self-refresh mode is smaller than current consumption during the refresh operation in a RAS-only refresh mode or a CAS-before-RAS refresh mode. In this technology, use or non-use of the memory is detected, and the refresh operation is performed in the RAS-only refresh mode or the CAS-before-RAS refresh mode when the memory is used and is performed in the self-refresh mode when the memory is not used, thereby reducing power consumption without causing the retained data to be lost.
However, this technology cannot be used for a DRAM which does not have the function of the self-refresh mode. Therefore, in a semiconductor device including a DRAM which does not have the self-refresh mode, a clock signal is generated by using the PLL circuit, and the refresh operation of the DRAM is performed based on the clock signal as described above. This makes it necessary to always operate the PLL circuit so that the PLL circuit and the refresh controller are operated even when it is desired to merely retain data without accessing the DRAM, whereby unnecessary current consumption occurs.